The existing Cu electrical interconnection film-forming process comprises, for instance, the step of forming a PVD-barrier film (such as PVD-Ti film or PVD-Ta film) and a PVD-seed film (PVD-Cu film) according to the consistent vacuum process (in-situ process) and the process also comprises, as subsequent steps, a Cu-plating step and a CMP step. However, the unsymmetrical properties, at the wafer edges, and the extent of the overhang of the PVD film thus formed increasingly become conspicuous on and after the generation in which the device node is on the order of 32 nm, due to the micronization of the size of the recent electrical interconnections or distributing wirings and as a result, a problem arises such that voids are formed during the plating step.
In this respect, the term “PVD-barrier film” used herein means a barrier film formed according to the PVD technique, while the term “PVD-seed film” herein used refers to a seed film prepared according to the PVD technique. The terms “PVD (CVD)-Cu film”, “ALD-barrier film” and “PVD (CVD, ALD)-Co film as used herein and appearing in the following description refer to films prepared according to the PVD, CVD and ALD techniques, respectively.
As shown in, for instance, FIGS. 1(a) and 1(b), if forming a PVD-seed film 103 (PVD-Cu film) on a barrier film 102 which has been applied onto the surface of a substrate 101 provided thereon with holes each having a diameter (φ) of 32 nm and trenches, the so-called overhang (the portion indicated by A) is caused at the upper portions of the holes and trenches and this in turn makes the openings of the holes or the like narrower. Then the interior of, for instance, the holes are filled up or buried with a Cu film 104 by the plating step, but various problems arise such that the presence of the foregoing overhang would prevent the easy introduction of a plating liquid into the interior thereof and that as the holes or the like is filled up or buried with the Cu film, the Cu film present therein is sucked up because of the insufficient adhesion between the Cu film and the barrier film and this correspondingly results in the formation of voids (the portion indicated by B) within the film. Moreover, as shown in FIGS. 1(c) and 1(d), a PVD-seed film 103 cannot be formed uniformly and symmetrically on the side face of, for instance, the holes (the portion indicated by C). This accordingly becomes a cause of a further problem such that voids (the portion indicated by D) would be generated in the Cu film 104 as will be formed during the subsequent plating step for filling up or burying the holes or the like, because of the foregoing unsymmetrical properties of the barrier film.
The barrier film formed according to the ALD technique or the CVD technique and the CVD-Cu film are free of any unsymmetricalness and they are not accompanied by overhanging and accordingly, it has been tried to form a Cu electrical interconnection film by a method which makes use of these two processes. In this case, however, the method suffers from a problem such that voids are formed in the resulting Cu film because of the insufficient adhesion between the CVD-Cu film and the ALD-barrier film as a base film. For this reason, such a method has not yet been put into practical use.
As shown in, for instance, FIGS. 2(a) and 2(b), when forming a TiN barrier film 202 according to the ALD technique (ALD-TiN barrier film) within the holes or trenches formed on a substrate 201 and then filling up or burying the interior thereof with a CVD-Cu film 203, voids (the portion indicated by the symbol A) are generated within the resulting Cu film. In this connection, FIG. 2(a) is an SEM micrograph showing the cross section of a substrate in which the holes or the like are filled up or buried with a CVD-Cu film 203, while FIG. 2(b) is a schematic diagram showing the same.
There have conventionally been proposed, as an adhesive layer used when forming a Cu-electrical interconnection film, films of Ti, Ru, Ru/Ti alloy, Cu/Ti alloy and Ru/Cu alloy prepared according to the CVD or ALD technique, and films of Ti, Ru, Ti/Ru alloy, Cu, Cu/Ti alloy and Cu/Ru alloy prepared according to the PVD technique (see, for instance, Non-Patent Document 1 specified below). In this respect, the production cost should be reduced as low as possible in the line for the mass production of semiconductor devices, but Ru as a rare metal is considerably expensive (next to gold and platinum) and therefore, the use thereof would increase the unit cost of producing the same. Thus, the use of such a metal is not suitable for the mass production. In addition, the use of Ti is not always acceptable since it does not necessarily have satisfied adhesive properties.
For this reason, there has been desired for the development of an adhesive film which can ensure the desired adhesion between the barrier film and the CVD-Cu film or PVD-Cu film and which can likewise ensure the merit of reducing the production cost, but there has not yet been developed any such a satisfactory adhesive layer.